In prior art circuits, such a delay is obtained by means of a D-type bistable. A distinction must then be made between low bit rates and high bit rates:
at low bit rates (.ltoreq.2 Mbit/s), metal oxide semiconductor (MOS) technology is used; shift registers having lengths of 64, 128, ..., 1024 bits are available in single 16-pin packages;
at higher bit rates, it is necessary to use fast particular "ECL 10000" or even "ECL 100 K".
However, since power consumption increases very fast with speed, and with the number of bistables, the number of D-type bistable per package decreases and it is difficult to obtain as many as 8 per package. This gives rise to too large a number of packages. For example, 128 packages each having 8 bistables are required for a delay of 1024 bits (128=1024/8); or 48 8bit packages are required to delay 6 binary trains by 64 bits (48=6.times.8).
Thus, whenever "n" and "m" are large, prior art circuits make use of a programmable divide-by-n counter in association with two identical random access memories (RAMs), with the binary counter sequentially addressing the data bits in one of the RAMs for writing purposes while simultaneously addressing the other RAM for reading purposes, and then sequentially addressing the RAMs for opposite purposes The desired delay is obtained by the division ratio (n) of the counter.
Such a circuit suffers from numerous drawbacks, and in particular:
it includes an address bus to be distributed;
it requires a multiplexer for large capacities since the input and the output to the data bus are then common and as a result additional registers need to be used; and
when switched on, the memories contain random values and as a result it is necessary to provide for an initialization stage in which a signal is sent to all possible address locations.